To reduce data redundancy in L1 data caches and L2 cache, we use low-cost and implementation-efficient base-delta-immediate (BDI) algorithm. Our work is motivated by the observation that the values within a cache block are similar, i.e., the arithmetic difference of two successive values within a cache block is small. We propose using cache compression to increase effective cache capacity, improve performance, and reduce power consumption in GPGPUs. GPGPU design trend shows that the size of caches continues to grow to support even more thread level parallelism. To handle working set of this massive number of threads, modern GPGPUs exploit several levels of caches. GPGPUs are throughput-oriented devices which execute thousands of threads simultaneously.

Our proposed scheme is geared toward improving performance and power of GPGPUs through cache compression. In this paper, we evaluate compressibility of L1 data caches and L2 cache in general-purpose graphics processing units (GPGPUs). Also, by analysis the models and results, we analyze the program estimator behavior with respect to micro-architecture parameters. Finally, we compare the our models with models of previous work by the help of this algorithm, and find out, that ,making models by more parameters and levels of values, help to more carefully explore in design space.

In this article, we defined design space NVIDIA Fermi GPU bigger than the prior similar work and with a 264 minimum size point, and we made performance prediction models by sampling only 45,000 design points from that, and then we offer an efficient search algorithm that carefully explore the design space by helping the performance models. Offering GPU performance prediction models base on Micro-architecture parameters to optimal design in the hardware process of the GPU, has been the subject of prior works. Recently, GPUs have also been used plenty in the scientific calculations for high-performance in parallel computing power and low energy consumption.

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